Modeling FIR to match Xilinx FIR IP

General usage
1

Trying to build up a model to match what is happening with the FIR IP in Xilinx. I am stuck on a few things.

  1. Building the main tap of the FIR I use a DLR, delay, and sum block. I am not sure how to model the finite characteristics with the DLR such as input and coefficient bits.

  2. There are many taps so what is the best way to convey that from scilab as variables?

  3. After building out the a tap I convert it to a super block. Is it best to save at that point as an xcos file and then add that to the pallet to build out the string of taps? I find the wiring start to get a little wonky even trying to follow the output to input methodology.

  4. After building out nested super blocks, I am not sure how to best pass variables. In each context for each super block? Gets pretty intense and hard to track.

Has anyone done this before and could help clear up a few things?