Inconsistency between delta block and register shift output

Specific domains Xcos
1

the block diagram below should output the same signal since a delay block is equivalent to a shift register and a clock.

Screenshot (151)
Screenshot (151)1645×667 27 KB

after running the simulation

note that for the delay block discretization time step =0.1
register initial state 10x0
the clock step linked with the shift register is also 0.1
and the shift register is initialized with 10x0

2

Hello,

Is it a continuous time simulation ?

S.

3

Hi,
yes it should be
how can I find out

4

Well, I am not sure about what Xcos does for this kind of diagram where there is no differential block. Did you try to increase the simulation time ?

5

OMG! I increased the simulation time from 5s to 50s and the two signals were identical
could you see the reason behind this?
thanks

6

maybe @davidcl could answer.

S.

7

Hi Yuri and welcome here,

This is a classic aliasing issue due to how Xcos/Scicos handle events. In your schema, you have two clocks with the same frequency but not synchronized. This is not a continuous schema in that aspect.

There are 3 events: the scope clock, the shift register clock and the pulse inner clock.
The scope clock will be propagated and applied to the delay and the mux.

To better understand, I suggest switching the scope to use marks instead of lines; you will then get the exact computation point.

To synchronize the clocks, either connect the shift register to a clock derived from the scope (using freq_div) or use a single shared clock with only SampleCLK blocks.

8

Dear davidcl,
thank you for being so helpful!
if I understand you well, a good practice is to use 1 clock per diagram
set this clock with high frequency to the scope, and then link it to other components via freq_divs.
please be advised when I deleted the shift clock and linked the shift register to the scope one, the problem persisted! This may be because I am using a low frequency to the scope which is violating the Nyquist-Shanon law.
as for SampleCLK I did not try it yet.
I am just seeking good practices to simulate the expected signal with the minimum computational price

9

Hi Yuri,

For discrete diagrams like yours, you should better use the SampleCLK everywhere. This guarantees you only have a single event thus you don’t have to fight against aliasing issues.