# LOGIC GATES in "red" wiring for XCOS

**URL:** https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573
**Category:** Xcos
**Created:** [June 28, 2024, 4:48pm UTC](https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573 "2024-06-28T16:48:30Z")
**Posts on this page:** 4
**Page:** 1

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### Author: ![Pascal77](https://avatars.discourse-cdn.com/v4/letter/p/a9a28c/32.png) [@Pascal77](https://scilab.discourse.group/u/Pascal77)
#### Post date: [June 28, 2024, 4:48pm UTC](https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573/1 "2024-06-28T16:48:30Z")

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Hello,

My question is related to logic gates. In the AND XCOS demo file, I have found a red AND gate. It looks like that:

![AND gate](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/e3561462095a8dcdaaa9cfd0dae95b77f21d22b7.png)

I need the OR gate, but I can’t find it.  
If someone knows something about it, thank you in advance.

Pascal 77

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### Author: ![mottelet](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/mottelet/32/13_2.png) [@mottelet](https://scilab.discourse.group/u/mottelet)
#### Post date: [June 29, 2024, 11:19am UTC](https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573/2 "2024-06-29T11:19:37Z")

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You have the generic logic block

![Capture d’écran 2024-06-29 à 13.18.18](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/e4560e6eb15272741ee1f03872063ed3c50735e8.png)  
which allows you to define an arbitrary binary boolean operator.

S.

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<div class="post-metadata">

### Author: ![Pascal77](https://avatars.discourse-cdn.com/v4/letter/p/a9a28c/32.png) [@Pascal77](https://scilab.discourse.group/u/Pascal77)
#### Post date: [June 30, 2024, 7:47pm UTC](https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573/3 "2024-06-30T19:47:56Z")

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Thanks Stéphane. I will try it. Your answer means that the expected block does not exist in XCOS? I mean this block:

![OR GATES in red wiring for XCOS - Specific domains _ Xcos - Scilab communit](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/2c218465d9b3b4a6c50e53541543b2d50bd611f7.png)

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<div class="post-metadata">

### Author: ![Pascal77](https://avatars.discourse-cdn.com/v4/letter/p/a9a28c/32.png) [@Pascal77](https://scilab.discourse.group/u/Pascal77)
#### Post date: [July 1, 2024, 2:27pm UTC](https://scilab.discourse.group/t/logic-gates-in-red-wiring-for-xcos/573/4 "2024-07-01T14:27:05Z")

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I found a block which is a kind of OR GATE (CLKSOMV\_f):  
 ![OR gate](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/e6df3c65e1530cfaba0519bf9f3413fc5e5527bb.png)

Now, I need the BOOLEAN NEGATION “NOT gate”. Something like that:  
 ![NOT](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/fe6b2dc92ccbb8e48a490a374cc328f591e01d55.jpeg)

According to me, a way of progress for XCOS should be to develop some boolean logic gates totally in the “red domain”. It should avoid to always switch between “black” and “red” .

At least, a NOT gate. After we can built any logic gate with NAND and NOT gates.

Pascal77