# Inconsistency between delta block and register shift output **URL:** \ **Category:** Xcos\ **Created:** [January 16, 2024, 10:47am UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342 "2024-01-16T10:47:29Z")\ **Posts on this page:** 9\ **Page:** 1
**Author:** ![yuri](https://avatars.discourse-cdn.com/v4/letter/y/71c47a/32.png) [@yuri](https://scilab.discourse.group/u/yuri)\ **Post date:** [January 16, 2024, 10:47am UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/1 "2024-01-16T10:47:29Z")
the block diagram below should output the same signal since a delay block is equivalent to a shift register and a clock. ![Screenshot (151)](https://global.discourse-cdn.com/free1/uploads/utc/original/1X/001c457bfbc23dd11d790d635294d469524531b3.png) after running the simulation note that for the delay block discretization time step =0.1 register initial state 10x0 the clock step linked with the shift register is also 0.1 and the shift register is initialized with 10x0 ---
**Author:** ![mottelet](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/mottelet/32/13_2.png) [@mottelet](https://scilab.discourse.group/u/mottelet)\ **Post date:** [January 16, 2024, 2:49pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/2 "2024-01-16T14:49:51Z")
Hello, Is it a continuous time simulation ? S. ---
**Author:** ![yuri](https://avatars.discourse-cdn.com/v4/letter/y/71c47a/32.png) [@yuri](https://scilab.discourse.group/u/yuri)\ **Post date:** [January 16, 2024, 3:06pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/3 "2024-01-16T15:06:14Z")
Hi, yes it should be how can I find out ---
**Author:** ![mottelet](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/mottelet/32/13_2.png) [@mottelet](https://scilab.discourse.group/u/mottelet)\ **Post date:** [January 16, 2024, 3:38pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/4 "2024-01-16T15:38:11Z")
Well, I am not sure about what Xcos does for this kind of diagram where there is no differential block. Did you try to increase the simulation time ? ---
**Author:** ![yuri](https://avatars.discourse-cdn.com/v4/letter/y/71c47a/32.png) [@yuri](https://scilab.discourse.group/u/yuri)\ **Post date:** [January 16, 2024, 3:41pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/5 "2024-01-16T15:41:48Z")
OMG! I increased the simulation time from 5s to 50s and the two signals were identical could you see the reason behind this? thanks ---
**Author:** ![mottelet](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/mottelet/32/13_2.png) [@mottelet](https://scilab.discourse.group/u/mottelet)\ **Post date:** [January 16, 2024, 3:44pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/6 "2024-01-16T15:44:15Z")
> [@yuri](#): > > could you see the reason behind this? maybe @davidcl could answer. S. ---
**Author:** ![davidcl](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/davidcl/32/1029_2.png) [@davidcl](https://scilab.discourse.group/u/davidcl)\ **Post date:** [January 16, 2024, 4:07pm UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/7 "2024-01-16T16:07:55Z")
Hi Yuri and welcome here, This is a classic aliasing issue due to how Xcos/Scicos handle events. In your schema, you have two clocks with the same frequency but not synchronized. This is not a continuous schema in that aspect. There are 3 events: the scope clock, the shift register clock and the pulse inner clock. The scope clock will be propagated and applied to the delay and the mux. To better understand, I suggest switching the scope to use marks instead of lines; you will then get the exact computation point. To synchronize the clocks, either connect the shift register to a clock derived from the scope (using **freq\_div** ) or use a single shared clock with only **SampleCLK** blocks. ---
**Author:** ![yuri](https://avatars.discourse-cdn.com/v4/letter/y/71c47a/32.png) [@yuri](https://scilab.discourse.group/u/yuri)\ **Post date:** [January 20, 2024, 6:04am UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/8 "2024-01-20T06:04:54Z")
Dear davidcl, thank you for being so helpful! if I understand you well, a good practice is to use 1 clock per diagram set this clock with high frequency to the scope, and then link it to other components via **freq\_div** s. please be advised when I deleted the shift clock and linked the shift register to the scope one, the problem persisted! This may be because I am using a low frequency to the scope which is violating the Nyquist-Shanon law. as for SampleCLK I did not try it yet. I am just seeking good practices to simulate the expected signal with the minimum computational price ---
**Author:** ![davidcl](https://yyz2.discourse-cdn.com/free1/user_avatar/scilab.discourse.group/davidcl/32/1029_2.png) [@davidcl](https://scilab.discourse.group/u/davidcl)\ **Post date:** [January 22, 2024, 7:51am UTC](https://scilab.discourse.group/t/inconsistency-between-delta-block-and-register-shift-output/342/9 "2024-01-22T07:51:06Z")
Hi Yuri, For discrete diagrams like yours, you should better use the SampleCLK everywhere. This guarantees you only have a single event thus you don’t have to fight against aliasing issues.